Wireless communication devices for receiving a radio signal have typically been arranged in such a manner that a received signal is converted to an analog demodulated signal by means of a predetermined arrangement, and this demodulated signal is binarized using a binarizing circuit so that an originally-transmitted radio signal is reconstructed.
An example of conventional binarizing circuits for binarizing a demodulated signal is described in reference to FIG. 10.
A binarizing circuit 41 includes a differentiating circuit 42 and a comparator 43.
The differentiating circuit 42 outputs a value corresponding to the slope of temporal variation of an input signal.
The comparator 43 compares the levels of respective input signals with each other, thereby outputting a signal corresponding to the result of the comparison. The comparator 43 compares the output from the differentiating circuit 42 with a signal with 0V (not illustrated), thereby outputting a value corresponding to the polarity of the output from the differentiating circuit 42.
Here, an example of signal waveforms in the binarizing circuit 41 is illustrated in reference to FIG. 11.
On the top of FIG. 11, an original binary data (original data) R on the side of the sender of a radio signal is illustrated for reference's sake.
In the middle of FIG. 11, a demodulated signal Q, which is an output signal from a demodulator 44, is illustrated. The demodulated signal Q is generated by demodulating a radio signal transmitted from a sender, the radio signal having been modulated from the foregoing binary data R.
On the bottom of FIG. 11, a data slicer output U which is an output signal from the binarizing circuit 41 is illustrated. The data slicer output U is generated by processing the demodulated signal Q in the differentiating circuit 42 and the comparator 43.
As illustrated in FIG. 10, a received signal N, which is obtained from an aerial, etc. (not illustrated), is converted to the demodulated signal Q in the demodulator 44, thereby inputted to the differentiating circuit 42. The output from this differentiating circuit 42 is supplied to the comparator 43. The comparator 43 carries out binarization according to the polarity of the signal supplied from the differentiating circuit 42, thereby outputting the data slicer output U.
As described above, it is possible to obtain the data slicer output U by binarizing the demodulated signal Q using the binarizing circuit 41.
Next, another example of the conventional binarizing circuits is described in reference to FIG. 12.
In the following description, members having the same functions as those described above are given the same numbers, so that the descriptions are omitted for the sake of convenience.
A binarizing circuit 45 is, as illustrated in FIG. 12, provided with a low-pass filter (LPF) 46 and a comparator 47.
The low-pass filter 46 removes a frequency component not less than a predetermined cutoff frequency from a supplied signal, thereby outputting only the remaining frequency component.
For instance, provided that the frequency component not less than the predetermined frequency is an alternating current component and the remaining frequency component is a direct current component, the low-pass filter 46 removes the alternating current component from the supplied signal and outputs the direct current component.
The comparator 47 compares the magnitudes of respective input signals with each other, thereby outputting a predetermined signal corresponding to the result of the comparison. The comparator 47 compares a demodulated signal Q outputted from the demodulator 44 with a slice level S outputted from the low-pass filter 46, thereby outputting a value corresponding to the result of the comparison.
Referring to FIGS. 13 and 14, an example of signal waveforms of the binarizing circuit 45 is illustrated as below.
On the top of FIG. 13, the respective temporal variations of the demodulated signal Q and the slice level S are illustrated. On the bottom of FIG. 13, the data slicer output U is illustrated.
On the top of FIG. 14, the demodulated signal Q and the slice level S are illustrated. On the bottom of FIG. 14, the data slicer output U is illustrated.
As illustrated in FIG. 12, a received signal N, which is obtained from an aerial, etc. (not illustrated), is converted to the demodulated signal Q in the demodulator 44. The demodulated signal Q is then supplied to the low-pass filter 46 and the comparator 47.
The low-pass filter 46 takes out the direct current component from the demodulated signal Q, thereby outputting the same as the slice level S.
The comparator 47 compares the demodulated signal Q with the slice level S so as to output a predetermined value in accordance with the result of the comparison, as a data slicer output U.
As described above, the binarizing circuit 45 binarizes the demodulated signal Q using the slice level S which varies in accordance with the magnitude of the demodulated signal Q so that the data slicer output U is obtained.
Next, a further example of the conventional binarizing circuits is described in reference to FIG. 15.
A binarizing circuit 48 is, as illustrated in FIG. 15, provided with a slice level detector circuit 49 and a comparator 50.
The slice level detector circuit 49 generates a slice level S according to a maximum hold value MAX and a minimum hold value MIN of a demodulated signal Q, thereby outputting the slice level S. This slice level detector circuit 49 will be specifically described later.
The comparator 50 compares the magnitudes of respective input signals with each other, thereby outputting a predetermined signal corresponding to the result of the comparison. The comparator 50 compares the demodulated signal Q with a slice level S, thereby outputting a value corresponding to the result of the comparison.
Now, the slice level detector circuit 49 is specifically described as below.
The slice level detector circuit 49 includes a maximum value detector circuit 51, a minimum value detector circuit 52, an adder circuit 53, and an amplifier 54.
The maximum value detector 51 detects the maximum value of a supplied signal and keeps the same, thereby outputting the value as a maximum hold value MAX. The minimum value detector circuit 52 detects the minimum value of the supplied signal and keeps the same, thereby outputting the value as a minimum hold value MIN. The adder circuit 53 adds up the supplied signals so as to produce an output. The amplifier 54 halves the level of the supplied signal so as to output the halved signal.
Now, an example of signal waveforms of the binarizing circuit 48 is described in reference to FIG. 16.
On the top of FIG. 16, an original binary data (original data) R on the side of the sender of a radio signal is illustrated for reference's sake.
On the middle of FIG. 16, a demodulated signal Q, which is an output signal from a demodulator 44, is illustrated. The demodulated signal Q is generated by demodulating a radio signal transmitted from the binarizing circuit 51, the radio signal having been modulated from the foregoing binary data R.
Other signals illustrated in the middle of FIG. 16 are: the maximum hold value MAX outputted from the maximum value detector circuit 51; the minimum hold value MIN outputted from the minimum value detector circuit 52; and a slice level S outputted from the slice level detector circuit 49.
On the bottom of FIG. 16, a data slicer output U which is generated from the demodulated signal Q and the slice level S in the comparator 50 is illustrated.
As in FIG. 15, a signal N, which is obtained from an aerial, etc. (not illustrated), is converted to the demodulated signal Q in the demodulator 44, thereby inputted to the slice level detector circuit 49 and the comparator 50.
In the slice level detector circuit 49, the maximum value detector circuit 51 and the minimum value detector circuit 52 output the maximum hold value MAX of the demodulated signal Q and the minimum hold value MIN of the demodulated signal Q, respectively.
The adder circuit 53 adds up the supplied maximum hold value MAX and minimum hold value MIN, so as to produce an output. The amplifier 54 halves the output of the adder circuit 53, i.e. halves the summation of the maximum hold value MAX and the minimum hold value MIN, so as to produce an output as the slice level S.
With these operations, the slice level detector circuit 49 outputs a value of (MAX+MIN)/2 as the slice level S.
The comparator 50 compares the supplied slice level S with the demodulated signal Q, and outputs a predetermined value according to the result of the comparison.
In this manner, it is possible to obtain the data slicer output U by binarizing the demodulated signal Q using the binarizing circuit 48.
As yet another example of the conventional binarizing circuits, the following will describe an arrangement taught by Japanese Laid-Open Patent Application No. 3-143012/1991 (Tokukaihei 3-143012; published on Jun. 18, 1991), in reference to FIG. 17.
A binarizing circuit 55 is, as illustrated in FIG. 17, provided with a maximum and minimum values detecting section 56, a maximum value keeping section 57, a minimum value keeping section 58, an intermediate level generation section 59, and a comparator 60.
Here, the difference between the binarizing circuit 55 and the binarizing circuit 48 is in that the maximum value keeping section 57 and the minimum value keeping section 58 are provided in the former circuit.
In the binarizing circuit 55, the comparator 60 corresponds to the comparator 50, the maximum and minimum values detecting section 56 corresponds to the maximum value detector circuit 51 and the minimum value detector circuit 52, and the intermediate level generation section 59 corresponds to the adder circuit 53 and the amplifier 54.
The maximum value keeping section 57 and the minimum value keeping section 58 figure out a maximum hold value and a minimum hold value in more precise manners, respectively. The values are figured out by setting respective time scales which are both different from that of the maximum and minimum values detecting section 56, in order to carry out the binarization more precisely.
The binarizing circuit 55 carries out the binarization through operations similar to those of the binarizing circuit 48 in FIG. 16.
As described above, it is possible to obtain the data slicer output U by binarizing the demodulated signal Q using the binarizing circuit 55.
However, in this arrangement, if the level of the demodulated signal is kept substantially consistent for a period longer than a predetermined time scale, the slice level follows this consistent level so that a detection error could occur when a noise is generated in the consistent level.
That is to say, in the arrangement in FIG. 11 which illustrates an example of the operation of the binarizing circuit 41 in FIG. 10, the following problem could occur.
In the example illustrated in FIG. 11, a noise is generated in the demodulated signal Q at a timing P1 because of a noise in the radio signal, and this causes an erroneous inversion of the data slicer output U at the timing P1.
This indicates that when a noise is detected on the occasion that the level of the demodulated signal Q is substantially consistent, an error could arise in the data slicer output U.
Further, since the temporal variation of the noise at the timing P1 has a shape causing diversion, the data slicer output U inverted at the timing P1 does not return to the value before the inversion.
Thus, until the demodulated signal is inverted again around a timing P2, errors arise in the data slicer output U at the timings P1 and P2.
In this manner, the binarizing circuit 41 using the differentiating circuit 42 could have such a problem that an error arises due to excessively sensitive response to a noise. Moreover, this could cause another problem such that the error which has been arisen is kept for a certain period of time and consequently a bit error rate (BER) deteriorates.
Further, in the binarizing circuit 45 in FIG. 12, the following problem could occur as illustrated in FIGS. 13 and 14.
As FIG. 13 illustrates, as in a portion between timings P3 and P5, the demodulated signal Q for binarization is occasionally kept at a consistent level for a predetermined period of time, according to the level of a transmitted signal (not illustrated).
The signal level S which is outputted from the low-pass filter 46 indicates a direct current level of the demodulated signal Q.
Thus, when the demodulated signal Q for binarization is kept at a consistent level for a predetermined period of time as in the portion between the timings P3 and P5, the slice level S comes close to the consistent level as indicated in a portion between the timings P4 to P5.
Here, the low-pass filter 46 is a member for outputting a frequency component not more than a cutoff frequency, as described above. For this reason, if, for instance, the demodulated signal Q is kept at a consistent level for one period of the cutoff frequency, the slice level S follows the demodulated signal Q. That is, one period of the cutoff frequency is equivalent to a time scale which causes the slice level S to follow the demodulated signal Q.
Thus, in this case the slice level S is substantially equal to the level of the demodulated signal Q as indicated in the portions between the timings P4 and P5 so that small noises in the demodulated signal Q could be detected, causing errors in the data slice output U indicated by a dotted line.
Further, as FIG. 14 illustrates, even in an arrangement opposite to the above, which, for instance, adopts a low-pass filter 46 whose cutoff frequency is lowered so that one period of the cutoff frequency is extended, the following problem could occur.
In this case, since the period necessary for causing the slice level S to follow the demodulated signal Q is extended as described above, the slice level S does not always follow the demodulated signal Q as in the portions between timings P6 and P7 in FIG. 14, and this could cause an error in the data slicer output U as in FIG. 14.
Thus, in the binarizing circuit in FIG. 12, since the low-pass filter 46 produces the time scale concerning the aforementioned following, errors due to the detection of noises are likely to occur as in FIG. 13 when the time scale is shortened, while an error on account of the slice level not following the demodulated signal is likely to occur as in FIG. 14 when the time scale is extended.
Further, when the aforementioned binarizing circuit 45 is included in a wireless communication device, a problem as below could occur. That is, the wireless communication device typically has a period in which no signal is received, such as a waiting time for a radio signal. Thus, when, for instance, a radio signal is received after a long waiting time, a slice level follows a false signal level in the waiting time, and hence errors could occur until the slice level correctly follows the level of a demodulated signal obtained from a signal received after the waiting time.
In the binarizing circuit 48 in FIG. 15, the problem as below could occur as illustrated in FIG. 16.
In the example in FIG. 16, in an original data R, a waiting time during which signals are neither transmitted nor received lasts until a timing P8. The original data R after the timing P8 corresponds to the header of a packet of outgoing data or incoming data.
As illustrated in FIG. 16, the slice level follows a demodulated signal generated by received noises, obstructive radio waves, etc during the waiting time, until the timing P8. In consequence, errors occur in the data slicer output, at the respective timings P8 and P9 which are immediately after starting to receive data.
During the waiting time until the timing P8, also the maximum hold value MAX and the minimum hold value MIN obtained in the respective circuits 51 and 52 could follow the demodulated signal Q generated by received noises and obstructive radio waves, causing the occurrence of errors.
That is to say, in the example of FIG. 16, the maximum hold value MAX is determined by a false maximum hold value during the waiting time so that an error occurs in the data slicer output U after a timing P10.
Since the operation of the binarizing circuit 55 illustrated in FIG. 17 is, as in the case of the binarizing circuit 48, also accompanied with a time scale of some kind, there is such a possibility that the slice level follows a false signal during a period for waiting the receipt of a correct signal, causing the occurrence of an error after starting the receipt.
As described above, the conventional binarizing circuits 41, 45, 48, and 55 are arranged such that, for instance, when a sequence of bits 0 is supplied as a radio signal or when a wireless communication device is in the state of waiting, the slice level follows a false signal so as to be kept at an undesired level, thereby causing the occurrence of errors.